The present invention relates to a nonvolatile semiconductor memory capable of changing memory cell data in units of bytes.
EEPROMs are conventionally known as nonvolatile semiconductor memories for changing memory cell data in units of bytes.
Reference 1 (W. Johnson et al., xe2x80x9cA 16 Kb Electrically Erasable Nonvolatile Memory,xe2x80x9d ISSCC Digest of Technical Papers, PP. 152-153, February 1982) has proposed an EEPROM which changes memory cell data in units of bytes using FLOTOX (Floating Gate Tunnel Oxide) cells.
FIG. 65 is a plan view showing an example of a memory cell section of an EEPROM capable of byte erase.
FIG. 66 is a sectional view taken along a line LXVIxe2x80x94LXVI in FIG. 65.
This EEPROM uses FLOTOX cells in the memory cell section. As a characteristic feature of a FLOTOX cell, an about 10-nm tunnel oxide film 22a is formed between an N+ drain 20a and a floating gate 21a, and charges are transferred between the N+ drain 20a and the floating gate 21a by applying an electric field to the tunnel oxide film 22a. 
A current flowing to the tunnel oxide film 22a is an F-N (Fowler-Nordheim) tunneling current generated by the F-N tunneling phenomenon.
FIG. 67 is a view showing the energy band of a MOS capacitor section.
When an electric field is applied to the MOS capacitor (N+ drainxe2x80x94tunnel oxide filmxe2x80x94floating gate), an F-N tunneling current flows to the tunnel oxide film (SiO2) on the basis of equation (1):                               I          =                                    S              ·              α              ·                              E                2                                      ⁢            exp            ⁢                          xe2x80x83                        ⁢                          (                                                -                  β                                /                E                            )                                      ⁢                  
                ⁢                              S            :   area                    ,                      E            :  electric  field                          ⁢                  
                ⁢                                                            α                =                                  xe2x80x83                                ⁢                                                                                                    q                        3                                            /                      8                                        ⁢                    π                    ⁢                                          xe2x80x83                                        ⁢                    h                    ⁢                                          xe2x80x83                                        ⁢                    Φ                    ⁢                                          xe2x80x83                                        ⁢                    B                                    =                                      6.94                    xc3x97                                          10                                              -                        7                                                              ⁢                                          xe2x80x83                                        ⁢                                          [                                              A                        /                                                  V                          2                                                                    ]                                                                                                                                              β                =                                  xe2x80x83                                ⁢                                                      -                    4                                    ⁢                                      xe2x80x83                                    ⁢                                      (                                          2                      ⁢                      m                                        )                                    ⁢                                      xe2x80x83                                    ⁢                  0.5                  ⁢                                      xe2x80x83                                    ⁢                  Φ                  ⁢                                      xe2x80x83                                    ⁢                  B                  ⁢                                      xe2x80x83                                    ⁢                                      1.5                    /                    3                                    ⁢                  hq                                                                                                        =                                  xe2x80x83                                ⁢                                  2.54                  xc3x97                                      10                    8                                    ⁢                                      xe2x80x83                                    ⁢                                      [V/cm]                                                                                                          (        1        )            
As is apparent from equation (1), the electric field with which the F-N tunneling current starts flowing is about 10 MV/cm. This electric field theoretically corresponds to a case wherein a voltage of 10V is applied to a tunnel oxide film of 10 nm.
Referring to FIGS. 65 and 66, assume that when a voltage is applied between the N+ drain 20a and a control gate 23a, the capacitance ratio (coupling ratio) between the control gate 23a and the floating gate 21a is 0.5.
In this case, to apply a voltage of 10V to the tunnel oxide film 22a between the N+ drain 20a and the floating gate 21a, a voltage as high as 20V must be applied between the N+ drain 20a and the control gate 23a. 
For example, in the erase mode, the N+ drain 20a is set at 0V and the control gate 23a at 20V to move electrons from the N+ drain 20a to the floating gate 21a. In the xe2x80x9c1xe2x80x9d program mode, the N+ drain 20a is set at 20V and the control gate 23a at 0V to move electrons from the floating gate 21a to the N+ drain 20a. 
The disadvantage of the EEPROM using FLOTOX cells is that two elements, a memory cell and a select transistor, are required to store 1-bit data, as shown in FIGS. 65 and 66.
FIG. 68 shows another example of the memory cell section of the EEPROM capable of byte erase.
As characteristic features of this EEPROM, FLOTOX cells are used in the memory cell section, and a byte control transistor Tr is prepared in correspondence with memory cells of 8 bits (1 byte).
Table 1 shows bias conditions in each mode of this EEPROM.
When such a memory cell section is used, various operation errors (disturbances) can be avoided. However, since 2+(xe2x85x9) transistors are required to store 1-bit data, the cell area increases to result in an increase in cost.
Flash EEPROMs aim at eliminating this problem. A conventional EEPROM is very convenient because data can be erased or programmed in units of 1-bit data.
However, when a computer hard disk requiring a large memory capacity is to be formed from an EEPROM, the EEPROM need not have a function of erasing or programming data in units of 1-bit data. In most hard disks, data is often erased or programmed in units of sectors (or in units of blocks).
It is more advantageous to attain a large memory capacity by cell area reduction and reduce the cost of products while omitting the function of changing data in units of 1-bit data. On the basis of such an idea, flash EEPROMs have been developed.
Details of a flash EEPROM are described in, e.g., reference 2 (F. Masuoka et al., xe2x80x9cA new Flash EEPROM cell using triple polysilicon technology,xe2x80x9d IEDM Technical Digest, pp. 464-467 December 1984).
FIG. 69 shows the structure of a memory cell of a flash EEPROM.
The memory cell of the flash EEPROM has a control gate and floating gate, like a memory cell of a UV erase EPROM. In the flash EEPROM, data is programmed by injecting hot electrons to the floating gate, as in the UV erase EPROM. Data is erased by removing electrons from the floating gate using the F-N tunneling phenomenon, like a byte EEPROM.
In the flash EEPROM, the erase operation for the individual memory cells is the same as in the byte EEPROM. However, the operation for the entire memory cell array is completely different from that in the byte EEPROM. More specifically, the byte EEPROM erases data in units of bytes while the flash EEPROM erases all bit data at once. Employing such an operation method, the flash EEPROM realizes a memory cell section with one transistor per bit and achieves a large memory capacity.
In the flash EEPROM, data can be programmed in units of bits, like the UV erase EPROM. More specifically, the flash EEPROM is the same as the UV erase EPROM in that all bit data are erased at once, and data can be programmed in units of bits.
To realize a memory chip with a large memory capacity, a NAND flash EEPROM has been proposed on the basis of the above-described flash EEPROM.
Reference 3 (F. Masuoka et al., xe2x80x9cNew ultra high density EPROM and Flash EEPROM with NAND structured cell,xe2x80x9d IEDM Technical Digest, pp. 552-555 December 1987) discloses a NAND flash EEPROM.
The memory cell array portion of a NAND EEPROM has a NAND unit in which a plurality of (e.g., 16) memory cells are serially connected to form a NAND series with select transistors connected to its two ends, respectively, as shown in FIGS. 70 and 71.
In the NAND EEPROM, a bit line contact section and source line need be formed not for each memory cell but for one NAND unit. Two adjacent memory cells of the plurality of memory cells forming the NAND series share one diffusion layer. For this reason, the memory cell size per bit can be largely reduced, and a memory chip having a large memory capacity can be realized.
FIG. 72 shows a NOR flash EEPROM. In the NOR flash EEPROM, a 1-bit (one) memory cell is formed between a bit line and a source line.
In terms of cost, the above-described NAND flash EEPROM has a characteristic feature suitable to a large-capacity file memory: the cost per bit is low because the cell size can be reduced as compared to the NOR flash EEPROM. In terms of function, the NAND flash EEPROM has a higher data change rate and lower power consumption than those of the NOR flash EEPROM.
In terms of function, the NAND flash EEPROM is characterized in the scheme for changing data. More specifically, the NAND flash EEPROM achieves program and erase by charge transfer between the silicon substrate (channel) and the floating gate.
To transfer charges, the F-N tunneling phenomenon is used. A current necessary for programming is an F-N tunneling current flowing from the silicon substrate (channel) to the floating gate. Unlike the NOR flash EEPROM that uses hot electrons for programming, the NAND flash EEPROM has very small current consumption.
In a 64-Mbit NAND flash EEPROM, data of one page (512 bytes) can be programmed in 200 xcexcs. This programming time is shorter than that for one block in the NOR flash EEPROM.
Table 2 shows comparison between the characteristic features of the NAND flash EEPROM and those of the NOR flash EEPROM.
As shown in Table 2, the advantages and disadvantages of these memories are complementary to each other.
For the application purpose, the NAND flash EEPROM is used aiming at changing data in units of blocks. For example, in a digital camera having 300,000 pixels requires a memory capacity of about 0.5 Mbit for a photograph of one shot. When one block of the NAND flash EEPROM has a memory capacity of about 0.5 Mbit or more, photograph data of one shot can be stored in one block. In this case, data is erased in units of blocks.
More specifically, photograph data of one shot is erased by erasing data of memory cells in one block.
On the other hand, the NOR flash EEPROM is capable of random access at a high speed of 100 ns and is widely used as a control program memory for, e.g., a portable telephone.
As described above, nonvolatile semiconductor memories have been developed as EEPROM (conventional type)xe2x86x92flash EEPROMxe2x86x92NAND flash EEPROM. The memory size, i.e., the cost per bit (bit cost) is reduced by sacrificing the function of changing data in units of bytes.
However, for, e.g., a nonvolatile memory embedded LSI which has received a great deal of attention recently, the function of changing data in units of bytes is required. For example, when an IC card used in a system for managing income and expenditure uses a flash EEPROM as an internal memory, data must be erased in units of blocks even when the data need a partial change. For this reason, the function of changing data in units of bytes is essential for such a system.
To cope with this situation, a byte EEPROM capable of changing data in units of bytes is required. However, the byte EEPROM has the large number of elements per bit, as described above, and therefore, is disadvantageous in increasing the memory capacity or reducing the bit cost.
Nonvolatile semiconductor memories of the current mainstream are flash EEPROMs (e.g., NOR type and NAND type). Hence, development of a byte EEPROM having the same process and scheme for changing data as those of a flash EEPROM makes it possible to produce EEPROMs meeting the requirements of the market at low cost.
The present invention has been made in consideration of the above situation, and has as its object to provide a new nonvolatile semiconductor memory which can be formed by the same process as that of a flash EEPROM, has the same scheme for changing data as in the flash EEPROM, and has a function of changing data in units of bytes.
According to the present invention, there is provided a nonvolatile semiconductor memory comprising a memory cell array having a memory cell unit formed from one memory cell and two select transistors sandwiching the memory cell, a bit line connected to one of the select transistors, and a sense amplifier connected to the bit line and having a latch function, wherein the memory cell has a stacked gate structure having a floating gate and a control gate.
According to the present invention, there is also provided a nonvolatile semiconductor memory comprising a memory cell array having a first memory cell unit formed from one memory cell and two select transistors sandwiching the memory cell and a second memory cell unit formed from a plurality of memory cells, a bit line commonly connected to the first and second memory cell units, and a sense amplifier connected to the bit line and having a latch function, wherein each of the memory cells has a stacked gate structure having a floating gate and a control gate.
The second memory cell unit comprises a NAND unit in which the plurality of memory cells are connected in series or an AND or DINOR unit in which the plurality of memory cells are connected in parallel.
Each of the two select transistors has the same structure as that of the memory cell. That is, each of the two select transistors has a stacked gate structure. Actually, of the upper and lower layers of the stacked gate structure, only, e.g., the lower layer functions as a gate electrode.
The nonvolatile semiconductor memory of the present invention further comprises means for, when data are to be changed for selected memory cells in memory cells of one page connected to a selected control gate line in the memory cell array, reading data of the memory cells of one page to the sense amplifiers, superscribing, in the sense amplifiers, data on data corresponding to the selected memory cells of the page, erasing the data of the memory cells of one page, and programming the data of the sense amplifiers in the memory cells of one page.
The data corresponding to the selected memory cells constitute byte data or page data.
According to the present invention, there is also provided a nonvolatile semiconductor memory comprising a memory cell array formed from memory cell units each including a memory cell, a bit line connected to the memory cell unit, a sense amplifier connected to the bit line and having a latch function, and means for, when data are to be changed for selected memory cells in memory cells of one page connected to a selected control gate line in the memory cell array, reading data of the memory cells of one page to the sense amplifiers, superscribing, in the sense amplifiers, data on data corresponding to the selected memory cells of the page, erasing the data of the memory cells of one page, and programming the data of the sense amplifiers in the memory cells of one page.
According to the present invention, there is also provided a nonvolatile semiconductor memory comprising a memory cell array having a memory cell for programming data using an F-N tunneling current, a bit line connected to the memory cell, a sense amplifier connected to the bit line and having a latch function, and means for, when data are to be simultaneously programmed in memory cells corresponding to one page, which are connected to a selected control gate line, applying a first potential to wells in which the memory cells of one page are formed, a second potential to a control gate of each of the memory cells of one page, the first potential to a bit line connected to a selected memory cell of the memory cells of one page, for which programming is to be executed, and an intermediate potential between the first and second potentials to a bit line connected to an unselected memory cell of the memory cells of one page, for which programming is not to be executed.
According to the present invention, there is also provided a nonvolatile semiconductor memory comprising a memory cell array formed from a plurality of memory cell units arranged in a matrix, a main control gate line extending in a row direction on the memory cell array, a main control gate driver at one end of the main control gate line, a sub control gate line connected to a plurality of memory cells of memory cells of one page in the memory cell units arranged in the row direction, and a sub control gate driver inserted between the main control gate line and the sub control gate line.
Each of the plurality of memory cell units is formed from one memory cell and two select transistors respectively connected to two ends of the memory cell.
The nonvolatile semiconductor memory of the present invention further comprises two select gate lines connected to gates of the two select transistors in each of the memory cell units arranged in the row direction, and a select gate driver connected to one end of each of the two select gate lines near the control gate driver.
The nonvolatile semiconductor memory of the present invention further comprises a sub decoder for decoding an address signal and outputting a control signal, and the sub control gate driver comprises a MOS transistor connected between the main control gate line and the sub control gate line and having a gate for receiving the control signal.
The nonvolatile semiconductor memory of the present invention further comprises a sub decoder for decoding an address signal and applying a predetermined potential to the sub control gate line, and the sub control gate driver comprises a MOS transistor connected between the sub control gate line and the sub decoder and having a gate for receiving the potential of the main control gate line.
The nonvolatile semiconductor memory of the present invention further comprises means for, when data are to be changed for arbitrary memory cells in memory cells of one page in the memory cell units arranged in the row direction, reading to the sense amplifiers data of the plurality of memory cells connected to the sub control gate line, superscribing, in the sense amplifiers, data on predetermined data of the data of the plurality of memory cells, erasing the data of the plurality of memory cells connected to the sub control gate line, and programming the data of the sense amplifiers in the plurality of memory cells connected to the sub control gate line.
The nonvolatile semiconductor memory of the present invention further comprises means for, when data are to be changed for arbitrary memory cells in memory cells of one page in the memory cell units arranged in the row direction, reading to the sense amplifiers data of memory cells of one page connected to the main control gate line, superscribing, in the sense amplifiers, data on predetermined data of the data of the plurality of memory cells connected to the sub control gate line, erasing the data of the plurality of memory cells connected to the sub control gate line, and programming, of the data of the sense amplifiers, data corresponding to the plurality of memory cells connected to the sub control gate line in the plurality of memory cells connected to the sub control gate line.
The sub control gate line is connected to memory cells of n bytes (n is a natural number), and data corresponding to the selected memory cells constitute byte data.
When the plurality of memory cells connected to the sub control gate line are defined as a block, a plurality of blocks are connected to the main control gate line, and a data read, erase, or program operation is performed in units of n (n is a natural number) blocks.
According to the present invention, there is also provided a nonvolatile semiconductor memory comprising a memory cell array formed from a plurality of memory cell units arranged in a matrix, first and second main control gate lines extending in a row direction on the memory cell array, a first main control gate driver connected to one end of the first main control gate line, a first sub control gate line connected to a plurality of memory cells of memory cells of one page in first memory cell units, which are arranged in the row direction, a first sub control gate driver inserted between the first main control gate line and the first sub control gate line, a first select gate line connected to a select transistor in each of the first memory cell units, a first select gate driver connected to one end of the first select gate line, a second main control gate driver connected to one end of the second main control gate line, a second sub control gate line connected to a plurality of memory cells of memory cells of one page in second memory cell units, which are arranged in the row direction, a second sub control gate driver inserted between the second main control gate line and the second sub control gate line, a second select gate line connected to a select transistor in each of the second memory cell units, and a second select gate driver connected to one end of the second select gate line, wherein the first main control gate driver and the first select gate driver are arranged at one end of the memory cell array in the row direction, and the second main control gate driver and the second select gate driver are arranged at the other end of the memory cell array in the row direction.
According to the present invention, there is provided a nonvolatile semiconductor memory comprising a memory cell array formed from a plurality of memory cell units arranged in a matrix, first and second main control gate lines extending in a row direction on the memory cell array, a first sub control gate line connected to a plurality of memory cells of memory cells of one page in first memory cell units, which are arranged in the row direction, a first sub control gate driver inserted between the first main control gate line and the first sub control gate line, a first select gate line connected to a select transistor in each of the first memory cell units, a first select gate driver connected to one end of the first select gate line, a main control gate driver connected to one end of each of the first and second main control gate lines, a second sub control gate line connected to a plurality of memory cells of memory cells of one page in second memory cell units, which are arranged in the row direction, a second sub control gate driver inserted between the second main control gate line and the second sub control gate line, a second select gate line connected to a select transistor in each of the second memory cell units, and a second select gate driver connected to one end of the second select gate line, wherein the main control gate driver and the first and second select gate drivers are arranged at one end of the memory cell array in the row direction.
The first and second memory cell units are, e.g., adjacent to each other in a column direction.
According to the present invention, there is provided a nonvolatile semiconductor memory comprising a memory cell array having first and second memory cell units each formed from one memory cell and two select transistors, a first bit line connected to one of the two select transistors in the first memory cell unit, a second bit line connected to one of the two select transistors in the second memory cell unit, and a sense amplifier connected to each of the first and second bit lines and having a latch function.
According to the present invention, there is also provided a nonvolatile semiconductor memory comprising a memory cell array having a memory cell unit formed from a plurality of memory cells and two select transistors sandwiching the memory cells, a bit line connected to one of the two select transistors, a sense amplifier connected to the bit line and having a latch function, and means for, in a program operation, applying a high program potential higher than a power supply potential to a selected control gate line and, to an unselected control gate line, the power supply potential or a read potential to be applied to the unselected control gate line in a read operation.
The memory cell unit includes two memory cells. Each of the plurality of memory cells has a stacked gate structure having a floating gate and a control gate.
Each of the two select transistors has the same structure as that of the plurality of memory cells.
According to the present invention, there is also provided a nonvolatile semiconductor memory comprising a memory cell array having a first memory cell unit formed from a plurality of memory cells and two select transistors sandwiching the memory cells and a second memory cell unit having a plurality of memory cells, a bit line commonly connected to the first and second memory cell units, a sense amplifier connected to the bit line and having a latch function, and means for, in a program operation, when a block including the first memory cell unit is selected, applying a high program potential higher than a power supply potential to a selected control gate line and, to an unselected control gate line, the power supply potential or a read potential to be applied to the unselected control gate line in a read operation.
The nonvolatile semiconductor memory of the present invention further comprises means for, when data are to be changed for arbitrary memory cells in memory cells of one page connected to a selected control gate line, reading data of the memory cells of one page to the sense amplifiers, superscribing, in the sense amplifiers, data on predetermined data of the page, erasing the data of the memory cells of one page connected to the selected control gate line, and programming the data of the sense amplifiers in the memory cells of one page connected to the selected control gate line.
In the program operation, the means applies the power supply potential or the read potential to the selected control gate line and the unselected control gate line and then increases only the potential of the selected control gate line to the high program potential.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.